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sa900 i/q transmit modulator preliminary specification 1997 sept 16 integrated circuits ic17 data handbook
philips semiconductors preliminary specification sa900 i/q transmit modulator do not distribute without ecn dated after sept 16, 1997 2 1997 sept 16 853- description the sa900 is a monolithic high performance, multi-function transmit modulator for use in cellular radio applications, fabricated in qubic bicmos technology. the sa900 features both analog (amps) mode and complex, i/q digital (nadc is136) mode quadrature modulation functions, a pll synthesizer with vco, crystal oscillator, programmable prescalers and gilbert cell multiplier phase detector with programmable charge pump output. the dualtx output can be used in dual mode cellular phone applications with the amps and nadc modulation being applied to the i/q baseband inputs. the dualtx output also provides 6-bit power control with 40db of gain control in 0.63db steps. in addition, buffered crystal oscillator programmable prescaler outputs are provided to support system clock reference needs. programming of the sa900 functions are realized by a high speed 3-wire serial interface. the sa900 can be programmed into a sleep mode (low current mode providing crystal oscillator and master clock functions), a standby mode (providing crystal oscillator, master clock, system clock 1 and transmit lo buffer functions), and the amps mode and the dual mode configurations. features ? v cc = 4.0v ? tx output frequency = 900mhz ? direct modulation of rf ? dual mode, on-chip pa control ? i/q modulator ? single sideband quadrature lo generation with no external adjustments required ? on-chip crystal oscillator with 3 buffered outputs ? amps/tacs compatible ? on-chip vco pin configuration be package 45 46 47 48 1 2 3 4 5 6 7 13 14 15 16 17 18 19 25 26 27 28 29 30 42 43 44 31 32 33 34 35 36 20 21 22 23 24 8 9 10 11 12 39 40 41 37 38 gnd txlo_2 txlo_1 gnd vcc tank_1 tank_2 vcc phsout gnd xtal_1 vcc gnd dualtx gnd vcc ampstx gnd vcc gnd vcc vcc gnd vcc lo_2 lo_1 gnd vcc i i q q gnd vcc gnd xtal_2 vcc clk1 gnd clk2 gnd mclk clkset data clock strobe txen i peak sr00636 figure 1. pin configuration ? selective power-down low power amps/tacs mode low power dual mode nadc ? 48-pin tqfp package applications ? north american digital cellular (tdma is-136) ordering information description temperature range order code dwg # 48-pin plastic low profile quad flat package (lqfp) -40 to +85 c SA900BE sot313-2
philips semiconductors preliminary specification sa900 i/q transmit modulator 1997 sept 16 3 block diagram 3/1 4/5/1 2/1 sm1 sm2 xy sm1 sm2 conv2 xtal osc control logic b8/1 a8/1 n bias lpf phs det lpf lpf vga control vga pa dualtx ampstx pa ad ad ad txen strobe clock data clkset mclk clk2 clk1 txlo_2 txlo_1 tank_1 tank_2 phsout i peak xtal_1 xtal_2 lo_2 lo_1 ii qq vco image reject mixer txlo vco se n<0:1> ad sm1 sm2 y x bg 2 6 ?? phase shift network sr00637 figure 2. block diagram
philips semiconductors preliminary specification sa900 i/q transmit modulator 1997 sept 16 4 pin descriptions pin description i non-inverting i mod signal i inverting i mod signal txlo_1/2 second lo input (differential/single-ended input) dualtx rf output (850mhz) digital (dual) mode, complex modulated output q non-inverting q mod signal q inverting q mod signal clk1 buffered oscillator output (xo 3/ 1) mclk buffered oscillator output (xo 4/ 5/ 1) clk2 buffered oscillator output (xo 2/ 1) ampstx rf output (850mhz) amps mode v cc +5v dc power supply gnd ground data serial data input clock serial clock input strobe data strobe input txen amps and dual mode transmit enable clkset program control pin for mclk prescaler xtal1 crystal oscillator base input xtal2 crystal oscillator emitter output phsout phase comparator charge pump output tank_1 vco differential tank tank_2 vco differential tank lo_1/2 buffered differential txlo output i peak phase comparator current programming
philips semiconductors preliminary specification sa900 i/q transmit modulator 1997 sept 16 5 1 4 11 16 18 25 28 30 33 35 37 39 45 48 5 8 14 27 29 32 36 38 44 26 gnd_lo gnd gnd gnd gnd gnd_ctrl gnd gnd gnd gnd gnd gnd gnd gnd 2 3 v cc _lo v cc _ctrl v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc 6 7 v cc v cc 9 v cc 0.1/6.4 ma 0.1/6.4 ma 12 13 v cc v cc 50 w 50 w sr00638 figure 3. pin diagrams
philips semiconductors preliminary specification sa900 i/q transmit modulator 1997 sept 16 6 19 v cc 17 15 20 v cc 500 w 24 v cc 500 w 23 22 21 31 v cc 30 w 34 600 w v cc 42 43 v cc v cc 40 41 680 w 680 w 47 v cc 46 20 w sr00639 figure 4. pin diagrams (cont.)
philips semiconductors preliminary specification sa900 i/q transmit modulator 1997 sept 16 7 absolute maximum ratings symbol parameter rating units v cc supply voltage -0.3 to +6 v v in voltage applied to any other pin -0.3 to (v cc + 0.3) v p d power dissipation, t a = 25 c (still air) 600 mw t jmax maximum operating junction temperature 150 c p max maximum power input/output +10 dbm t stg storage temperature range 65 to +150 c note: 1. maximum dissipation is determined by the operating ambient temperature and the thermal resistance, q ja . 48-pin lqfp: q ja = 67 c/w recommended operating conditions symbol parameter rating units v cc supply voltage 3.9 to 5.1 v t a operating ambient temperature range -40 to +85 c t j operating junction temperature -40 to +105 c dc electrical characteristics v cc = +4.0v, t a = 25 c; unless otherwise stated. symbol parameter test conditions limits units symbol parameter test conditions min typ max units v cc power supply range 3.9 5.1 v sleep mode 3.1 i cc su pp ly current standby mode 8.2 ma i cc s u ppl y c u rrent amps mode 27.5 ma dual mode 64 i / i in-phase differential baseband input dc 0.5v cc v q / q quadraphase differential baseband input dc 0.5v cc v 4 v cc clkset divide by 4/5/1 5 0.5v cc v 1 0 v il clock, data, strobe, txen input low 0.3 0.3v cc v v ih clock, data, strobe, txen input high 0.7v cc v cc +0.3 v
philips semiconductors preliminary specification sa900 i/q transmit modulator 1997 sept 16 8 ac electrical characteristics v cc = +4.0v, t a = 25 c; tank_1 = 120mhz @ 0 dbm; xo_ref = 30mhz @ 5 dbm; txlo2 = 13 dbm, unless otherwise stated. symbol parameter test conditions limits units symbol parameter test conditions min typ max units input power -13 -10 1 dbm txlo_1/2 transmit lo input (ac couple) (50 w ) vswr (50 w ) 2:1 dbm frequency range 900 1040 mhz tank_1/2 vco tank differential inputs frequency range 90 1 120 140 1 mhz phsout phase detector charge pump output output level 0.5 v cc 0.5 v i phsout p rogramming r set = 24k w , ad=0 200 300 400 m a i peak phsout programming r set = 24k w , ad=1 0.9 1.2 1.5 ma xtal 1 xo transistor base xo frequency 10 1 30 45 1 mhz xtal _ 1 xo transistor base external drive 150 1 350 500 1 mv p-p clk1 xo divide 3/1, power down sm1=0, 50% duty cycle frequency range 3.33 1 30 45 1 mhz 3, x=1, 1, x=0 output level, 5k w || 7pf 0.7 1 1.4 v p-p clk2 xo divide 2/1, power down sm2=0 frequency range 5 1 30 45 1 mhz clk2 2, y=1, 1, y=0 output level, 5k w || 7pf 0.7 1 1.4 v p-p xo divide 4/5/1, 50% duty cycle frequency range 2 1 45 1 mhz mclk 4, clkset = v cc , 5, clkset = 0.5v cc , 1, clkset = 0v output level, 5k w || 7pf 0.7 1 1.4 v p-p serial data clock input, 33% duty cycle max clock rate 10 1 mhz clock serial interface (cmos levels) logic low 0.3v cc 1 v data, clock, strobe, txen logic high 0.7v cc v amps output, se=1, ad=0, txen=1 (ac couple) frequency range 820 860 mhz vswr 2:1 output level 1.5 +2 dbm 869 to 894mhz -104 dbm 824 to 849mhz -47 dbc ampstx spurious output 2 to 824mhz -41 dbc 849 to 869mhz -41 dbc 894mhz to 8.49ghz -41 dbc txlo and harmonics -21 dbc adjacent channel noise power @30khz -95 dbc/hz alternate channel noise power @60khz -101 dbc/hz broadband noise power 869 to 894mhz -136 dbm/hz dual output, se=1, ad=1, txen=1 (with external matching figure 9) frequency range 820 920 2 mhz dualtx vswr 2:1 dualtx output level (avg) (i and q quad, 0db vga) 0 +2 dbm gain flatness 1 db
philips semiconductors preliminary specification sa900 i/q transmit modulator 1997 sept 16 9 ac electrical characteristics (continued) symbol parameter test conditions limits units symbol parameter test conditions min typ max units dualtx 3rd order -35 -42 dbc (cont.) linearity (0db vga, i and q inphase) 5th order -55 dbc 7th order -65 dbc carrier suppression (i and q quadrature) vga = 0db -35 -45 dbc carrier suppression (i and q quadrature) vga = 40db -28 -33 dbc sideband suppression i and q quadrature -35 -45 dbc 869 to 894mhz 104 dbm 824 to 849mhz 47 dbc spurious output 2 to 824mhz 41 dbc 849 to 869mhz 41 dbc 894mhz to 8.49ghz 41 dbc txlo and harmonics 21 dbc broadband noise (0db vga) 869 to 894mhz 136 dbm/hz broadband noise (0db vga) 935 to 960mhz 136 dbm/hz adjacent channel noise power @30khz 95 dbc/hz alternate channel noise power @60khz 101 dbc/hz max frequency 0.8 2 1 mhz q/q baseband quadrature differential input differential modulation level 0.6 1 0.8 1.0 1 v p-p differential input impedance 10 1 k w max frequency 0.8 2 1 mhz i/i baseband inphase differential input differential modulation level 0.6 1 0.8 1.0 1 v p-p differential input impedance 10 k w buffered txlo differential outputs (ac coupled) frequency range 900 1040 mhz vswr (single-ended) 2:1 lo_1/2 out p ut im p edance single-ended 50 w _ o u tp u t impedance differential 100 w out p ut level single-ended, 50 w 50 90 mv p-p out ut level differential, 100 w 100 180 mv p-p notes: 1. guaranteed by design. 2. needs a different matching component. max test frequency is 850mhz with test circuit shown in figure 11. functional description dual mode operation the sa900 transmit modulator provides direct single sideband quadrature modulation of the difference of the txlo and vco frequencies, while providing quadrature lo signals for the i/q modulator. the quadrature lo signals are modulated with high linearity by the baseband inphase (i) and quadrature (q) signals. the summed modulator output produces the lower sideband, while rejecting the upper sideband. the i and q inputs also provide dc biasing for the modulator inputs. the summed output of the modulator goes to a variable gain amplifier (vga) to control the output level, it has 40.0db of attenuation control range, with 0.63db steps. the power control function is programmed by means of a 6-bit word (see table 3). the vga output drives the power amp output stage to provide +2dbm average minimum power level (at 0db power control) into 50 w , in conjunction with external matching components on dualtx. the ad (amps/dual) and the se (synthesizer enable) bit control the power up/down of the dual mode function. the transition of the txen, from low to high turns on the modulator. the falling edge of the txen signal disables the synthesizer and modulator. the txlo is a system supplied lo signal. the sa900 buffers the txlo signal (lo_1/2) for use with the system synthesizer (such as the sa7025) to form the system lo synthesizer loop. the dual mode can also be used for amps operation. the amps and dual mode modulation is generated by the system dsp ic to provide the required i/q baseband modulation for the sa900. the dual output provides low broadband noise output power (so that the receiver sensitivity is not degraded) and high linearity to meet cellular phone system needs. table 1 provides the vga power control limits. the sa900 dualtx output is externally matched with either a shunt inductor to v cc and a series capacitor or a shunt inductor to v cc and a series inductor. this matches the dualtx output to 50 w . values of the matching components are dependent on pcb layout, typical values are shown in figure 9.
philips semiconductors preliminary specification sa900 i/q transmit modulator 1997 sept 16 10 table 1. vga power control limits vga min. typ. max. relative vga 0 0 0 0 0 1 -1 -.63 -.2 0 2 -1 -.63 -.2 1 3 -1 -.63 -.2 2 4 -1 -.63 -.2 3 5 -1 -.63 -.2 4 6 -1 -.63 -.2 5 7 -1 -.63 -.2 6 15 -6.6 -5 -3 7 23 -6.6 -5 -3 15 31 -6.6 -5 -3 23 39 -6.6 -5 -3 31 47 -6.6 -5 -3 39 55 -6.6 -5 -3 47 63 -6.6 -5 -3 55 63 -43.2 -40.4 -37.2 0 1. guaranteed to be monotonic. amps mode operation the sa900 can be configured to operate in the amps mode, where fm modulation is applied to the sa900's vco. for the amps mode, the vco is configured with the proper synthesizer bandwidth to allow the application of the amps modulation to the vco varactor tuned tank circuit. the modulated vco signal is input into an image reject mixer along with the txlo signal, where the upper sideband is rejected. this single sideband modulated signal then drives the amps output power amplifier. the pa provides +2dbm power level into 50 w , with no external matching components required. the ad (amps/dual) and the se (synthesizer enable) bit control the power up/down of the amps mode function. the transition of the txen signal from low to high turns on the modulator. the falling edge of txen signal disables the synthesizer and the modulator. synthesizer operation the sa900 synthesizer is comprised of the differential vco circuit, with external tank components, the gilbert cell multiplier phase detector with programmable charge pump current, crystal oscillator and programmable prescalers. the charge pump output drives an external second order loop filter. the output of the loop filter is used to provide the control voltage to the vco tuning varactor to complete the pll synthesizer. the synthesized vco output frequency is mixed with the txlo signal to generate the transmit lo from the lower sideband (the difference of the vco and txlo frequencies). the output of vco is fed to a programmable /n prescaler with user selectable divides of 6, 7, 8 and 9 (all divides configured to provide 50% duty cycle). the output of the /n divider drives the a8/1 prescaler. the a8/1 divide is selected by the ad control bit (ad=1 for /1, and ad=0 for /8). the output of the divide a8/1 is fed into one input of the phase detector. the reference input for the phase comparator is generated from the crystal oscillator (xo) output from the b8/1 prescaler. the b8/1 divide is selected by the ad control bit (ad=0 for /8, and ad=1 for /1). the phase detector compares the prescaled xo reference phase to the vco prescaled phase, to generate a charge pump output current proportional to the phase error. the phase detector, a gilbert cell multiplier type, having a linear output from 0 to p ( p /2 p /2). the charge pump peak output current is programmable from 100 m a for the amps mode (ad=0) to a maximum of 6.4ma for the dual mode (ad=1) by way of an external current setting resistor placed from i peak to circuit ground. the typical loop filter network is shown in figure 5. the charge pump current output is programmed by ad 0i out 6 1.25v r set ad 1i out 24 1.25v r set where r set is placed between i peak and ground. the pll frequency is determined by vco xo n ( a8 1 ) ( b8 1 ) where n=6, 7, 8, 9 and a8/1 and b8/1 are controlled by the ad bit (ad=1 a8/1 and b8/1 are divide by 1, ad=0 a8/1 and b8/1 are divide 8). table 2. data word format mnemonics bits function a0 1 (msb) address bit 0 (1) a1 2 address bit 1 (0) a2 3 address bit 2 (1) a3 4 address bit 4 (1) pc0 5 power control bit 0 pc1 6 power control bit 1 pc2 7 power control bit 2 pc3 8 power control bit 3 pc4 9 power control bit 4 pc5 10 power control bit 5 n0 11 divide n bit 0 n1 12 divide n bit 1 ad 13 amps/dual mode select bit se 14 synthesizer enable bit na 15 na sm1 16 sleep mode 1 control bit sm2 17 sleep mode 2 control bit x 18 divide 3/1 control bit y 19 divide 2/1 control bit na 20 na na 21 na na 22 na na 23 na na 24 (lsb) na vco operation the vco is designed to operate from 90mhz to 140mhz. the vco tank is configured using a parallel inductor and a dual common cathode tuning varactor diodes. dc blocking capacitors are used to isolate the varactor
philips semiconductors preliminary specification sa900 i/q transmit modulator 1997 sept 16 11 control voltage from the vco tank dc bias voltages. the vco tuning voltage is generated from the output of the pll loop filter. the vco tank configuration is shown in figure 6. crystal oscillator (xo) operation for cellular radio applications, the sa900 will most likely utilize an external reference tcxo in order to provide the frequency stability necessary to operate to system requirements. the output of the system tcxo can be ac coupled to the xtal_1 input. however, for applications that do not require such accuracy the xo circuit can be configured as a colpitts type oscillator with the addition of two external capacitors along with the reference crystal and a trim capacitor as shown in figure 7. programmable clock outputs the sa900 generates three buffered xo outputs used for external reference signals. the xo feeds three sets of programmable prescalers, the prescaler outputs are buffered to provide the clk1, clk2 and mclk signals. the clk1 signal is a selectable divide 3/1 (x=1 divide 3, x=0 divide 1), 50% duty cycle, of the xo reference signal. the clk2 signal is a selectable divide 2/1 (y=1 divide 2, y=0 divide 1), 50% duty cycle, of the xo reference signal. the mclk signal is a selectable divide 4/5/1 (clkset = v cc divide 4, clkset = v cc /2 divide 5, and clkset = 0v divide 1), 50% duty cycle, of the xo reference signal. mclk is externally set by means of the tri-level clkset input to provide a default master system clock prior to programming the sa900. programming operation the sa900 is configured by means of a 3-wire input (clock, strobe, data) to program the amps and dual modes, in addition there are two power saving modes of operation, sleep and standby. the control logic section of the sa900 is designed using low power cmos logic. during sleep mode only the circuitry required to provide a master clock (mclk) to the digital portion of the system is enabled. during the standby mode of operation mclk, clk1 and the txlo and buffered lo outputs are powered on, which may be the case when the system is in the receive only mode. in the amps or dual operational modes all functions of the sa900 are powered on to support receive, transmit and system clock functions. the programming of the sa900 is identical to the programming format of the sa7025 low-voltage 1ghz fractional-n synthesizer, that can be used in conjunction with the sa900 to provide the cellular radio channel selection. the programming data is structured as a 24 bit long serial data word; the word includes 4 address bits (dedicated 1 0 1 1) for chip select. data bits are shifted in on the leading edge of the clock, with the least significant bit (lsb) first and the most significant bit (msb) last. table 2 shows data word format, the 15th and last 5 bits are not used. figure 8 shows the chip timing diagram. address a0 a1 a2 10 1 a3 1 divide by n n0 n1 divide 00 6 10 7 01 8 11 9 amps/dual mode the a/d mode select enables or disables that portion of the circuitry used for either the amps or dual mode of operation. ad mode 0 amps 1 dual synthesizer enable the se bit turns on and off the synthesizer circuitry. se operation 0 disabled 1 enabled sleep mode 1 the sm1 bit is used to power down the txlo buffer, the divide 3/1 prescaler and the clk1 output buffer. sm1 operation 0 power down 1 power up (standby) sleep mode 2 the sm2 bit is used to power down the divide 2/1 prescaler and the clk2. sm2 operation 0 power down 1 power up (with sm1=1 normal operation) divide 3 x operation 0 divide 1 1 divide 3 divide 2 y operation 0 divide 1 1 divide 2
philips semiconductors preliminary specification sa900 i/q transmit modulator 1997 sept 16 12 table 3. power control attenuation (db) pc0 (0.6db) pc1 (1.3db) pc2 (2.5db) pc3 (5.0db) pc4 (10.0db) pc5 (20.0db) 0 0 0 0 0 0 0 0.6 1 0 0 0 0 0 1.3 0 1 0 0 0 0 1.9 1 1 0 0 0 0 2.5 0 0 1 0 0 0 3.2 1 0 1 0 0 0 3.8 0 1 1 0 0 0 4.4 1 1 1 0 0 0 5.0 0 0 0 1 0 0 5.7 1 0 0 1 0 0 6.3 0 1 0 1 0 0 ? ? ? 23.3 1 0 1 0 0 1 ? ? ? 39.7 1 1 1 1 1 1 component value r1 560 w designator dual mode amps mode r2 1k w c1 2.2nf c2 no load c3 33pf 560 w 5.6k w 2.7 m f .27 m f 6.8nf phsout r2 r1 c1 c2 c3 v ctrl typical filter network r set 15k w 75k w sr00640 figure 5. pll loop filter l1 (amps modulation) tank_1 v ctrl tank_2 v cc c3 c2 c1 vr1 f vco 120mhz 1 2 l1c c c3 1 c1 1 c2 1 cvri 1 c1 = c2 = 33pf c3 = 12pf l1 = 82nh vr1 toko kv1470 sr00641 figure 6. vco tank configuration
philips semiconductors preliminary specification sa900 i/q transmit modulator 1997 sept 16 13 xtal_1 xtal_2 c2 c1 xo cvar sr00642 figure 7. crystal oscillator configuration txen data clock strobe syn_en lsb msb t1 t2 t3 transmit enabled synthesizer enabled t4 t1 t2 t3 1 3clock ,t 4 1 3clock sr00643 figure 8. chip timing diagram v cc sa900 l1 34 l2 1000pf 50 w 1nf 100pf typical values l1 = 39nh l2 = 22nh or v cc sa900 l3 34 c1 50 w 1nf 100pf typical values l3 = 12nh c1 = 1.5pf sr00644 figure 9. dualtx output matching
philips semiconductors preliminary specification sa900 i/q transmit modulator 1997 sept 16 14 q1 i2 i1 j3 j4 j5 j6 c241 100pf c305 100pf c306 .010uf l304 39nh c301 100pf l372 22nh c242 100pf 1 2 w4 zo=50 j9 digtxrf j10 ampstxrf 12 w5 zo=50 c312 100pf c300 .010uf jp1 jmp jp2 jmp jp3 jmp r349 100k r350 100k c245 .010uf q2 1 2 w1 zo=50 1 2 w2 zo=50 j8 lo2ps1 j7 lo2ps2 vcc c246 gnd p1-4,5,6,11,12,13 p1-1,2,3 4.7uf + c247 100pf c313 100pf c314 100pf j1 txlo2 12 w3 zo=50 c249 100pf jp4 jmp vco-tune p1-15 phs-out p1-14 jp5 jmp c269 33pf r264 1k r333 1k r258 1k c254 33pf d1 kv1470 c255 33pf c253 5.6pf l252 100nh r266 560 r268 nl c267 220pf c265 nl j18 vco-ref t1-1 kk81 j2 xo-ref r274 0 r260 51 r284 nl c263 .01uf c371 100pf r352 100 100pf c370 r262 15k c243 100pf r279 nl c299 nl c283 nl c282 nl l280 nl c281 .010uf c287 .010uf r293 nl c292 nl c289 nl l290 nl p2 clk1 p3 clk1 c288 .010uf p4 mclk l296 nl c295 nl c294 nl r297 nl 1 2 3 4 5 6 7 8 9 10 11 12 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 36 35 34 33 32 31 30 29 28 27 26 25 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 vcc gnd dualtx gnd vcc ampstx gnd vcc gnd vcc vcc gnd gnd txlo2 txlo1 gnd vcc tank1 tank2 vcc phs out ipeak gnd xtal1 v c l o l o g n v c i 1 i 2 q 1 q 2 g n v c g n c21dc d d c x v c g c g m c d c s t t a l 1 c c l k 1 n d l k 2 n d c l k l k s e t a t a l o c k t r o b e x e n u1 SA900BE p1-7 data p1-8 clock p1-9 strobe p1-10 txenable note: vco-ref circuit is optional l372 is c307 on the pcb c246 combines c240 and c244 on the pcb sr00645 figure 10. sa900 application circuit
philips semiconductors preliminary specification sa900 i/q transmit modulator 1997 sept 16 15 q1 i2 i1 c241 100pf c305 100pf c306 .010uf l304 39nh c301 100pf l372 22nh c242 100pf 1 2 zo=50 digtxrf c300 .010uf c245 .010uf q2 vcc c246 gnd 1000pf + c247 270pf txlo2 12 w3 zo=50 c249 100pf tank1 t1-1 kk81 xo-ref r260 51 c263 .01uf c371 100pf 100pf c370 c243 100pf 1 2 3 4 5 6 7 8 9 10 11 12 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 36 35 34 33 32 31 30 29 28 27 26 25 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 vcc gnd dualtx gnd vcc ampstx gnd vcc gnd vcc vcc gnd gnd txlo2 txlo1 gnd vcc tank1 tank2 vcc phs out ipeak gnd xtal1 v c llg n v c i 1 i 2 q 1 q 2 g n v c g n cdc dd c x vgg cd c s t t a l 1 c c n d n d l k 2 a t a l o c k t r o b e x e n data clock strobe txenable o 1 o 2 sa900 r301 1k c280 1000pf r300 1k phase out r262 24k r304 4.7k c402 7pf clock2 c l k 1 r303 4.7k c400 7pf clock1 m c l k r305 4.7k c401 7pf mclk clkset c l k s e t c312 100pf 1 2 zo=50 ampstx c315 270pf 1 2 zo=50 lo_1 c314 270pf 1 2 zo=50 lo_2 sr00646 figure 11. sa900 test circuit
philips semiconductors preliminary specification sa900 i/q transmit modulator 1997 sept 16 16 performance characteristics 900 970 1040 16.00 frequency (mhz) power (dbm) lo buffer vs. frequency (27 c, txlo = 10dbm) 16.50 17.00 17.50 18.00 18.50 19.00 900 970 1040 16.00 frequency (mhz) power (dbm) lo buffer vs. frequency (v cc = 4.0v, txlo = 10dbm) 16.50 17.00 17.50 18.00 18.50 19.00 19.50 20.00 t = +85 c t = +27 c t = 45 c v cc = 3.9v v cc = 4.0v v cc = 4.5v 820 836 860 3.00 frequency (mhz) power (dbm) amptx vs. frequency (27 c, txlo = 10dbm) 2.80 2.60 2.40 2.20 2.00 1.80 1.60 1.40 1.20 1.00 v cc = 3.9v v cc = 4.0v v cc = 4.5v 820 836 860 4.00 frequency (mhz) power (dbm) amptx vs. frequency (v cc = 4.0v, txlo = 10dbm) 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0.50 1.00 820 836 850 2.60 2.40 2.20 frequency (mhz) power (dbm) dualtx vs. frequency (temp 27 c, txlo = 10dbm) 820 836 850 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 frequency (mhz) power (dbm) dualtx vs. frequency (v cc = 4.0v, txlo = 10dbm) 40 27 85 72 70 68 66 64 62 60 current (amperes) dual i cc vs. temperature temperature ( c) t = +85 c t = +27 c t = 45 c sr00647 2.80 2.00 v cc = 4.5v v cc = 3.9v v cc = 4.0v v cc = 4.5v v cc = 4.0v v cc = 3.9v v cc = 40 c v cc = 27 c v cc = 85 c figure 12. performance characteristics
philips semiconductors preliminary specification sa900 i/q transmit modulator 1997 sept 16 17 performance characteristics 820 836 850 43.00 44.00 44.50 45.00 45.50 46.00 46.50 suppression (dbc) dualtx carrier suppression vs. frequency (v cc = 4.0, txlo = 10dbm single sideband mode, with respect to lower sideband) frequency (mhz) 47.50 47.00 820 836 850 44.50 45.00 45.50 46.00 47.00 47.50 suppression (dbc) dualtx sideband suppression vs. frequency (temperature = 27 c, txlo = 10dbm single sideband mode, with respect to lower sideband) frequency (mhz) 820 836 850 34.00 frequency (mhz) suppression (dbc) dualtx sideband suppression vs frequency (v cc = 4.0v, txlo = 10dbm single sideband mode, with respect to lower sideband) 40 27 40 41 42 dbc dualtx 3rd order products vs temperature (txlo = 10dbm, f = 836mhz, 0db vga i/q inphase) temperature ( c) 85 0 30.00 attenuation (db) dualtx carrier suppression vs vga range (27 c, f = 836mhz, txlo = 10dbm) vga 6-bit word value (lsbs) 35.00 40.00 45.00 50.00 55.00 2 5 7 101315182023252629333740444851555963 0 30.00 attenuation (db) dualtx carrier suppression vs vga range (v cc = 4.0v, f = 836mhz, txlo = 10dbm) vga 6-bit word value (lsbs) 35.00 40.00 45.00 50.00 55.00 257101315182023252629333740444851555963 60.00 v cc = 3.9v v cc = 4.0v v cc = 4.5v 36.00 38.00 40.00 42.00 44.00 46.00 48.00 t = +85 c t = +27 c t = 45 c sr00648 43.50 46.50 37 38 39 34 35 36 33 32 v cc = 40 c v cc = 85 c v cc = 27 c v cc = 4.5v v cc = 4.0v v cc = 3.9v v cc = 85 c v cc = 40 c v cc = 27 c v cc = 3.9v v cc = 4.0v v cc = 4.5v figure 13. performance characteristics
philips semiconductors preliminary specification sa900 i/q transmit modulator 1997 sept 16 18 performance characteristics 02 0 attenuation (db) dualtx vga attenuation profile vs. temperature (v cc = 4.0v, f = 836mhz) vga 6-bit word value (lsbs) 468 5 10 15 20 25 30 35 40 45 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 40 c 02 attenuation (db) dualtx vga attenuation profile vs. v cc (t = 27 c, f = 836mhz) vga 6-bit word value (lsbs) 468 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 sr00649 27 c 85 c 3.9v 0 5 10 15 20 25 30 35 40 45 4.0v 4.6v figure 14. performance characteristics
philips semiconductors preliminary specification sa900 i/q transmit modulator 1997 sept 16 19 lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
philips semiconductors preliminary specification sa900 i/q transmit modulator 1997 sept 16 20 philips semiconductors and philips electronics north america corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performanc e. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under a ny patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copy right, or mask work right infringement, unless otherwise specified. applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. life support applications philips semiconductors and philips electronics north america corporation products are not designed for use in life support appl iances, devices, or systems where malfunction of a philips semiconductors and philips electronics north america corporation product can reasonab ly be expected to result in a personal injury. philips semiconductors and philips electronics north america corporation customers using or sel ling philips semiconductors and philips electronics north america corporation products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors and philips electronics north america corporation for any damages resulting from such improper use or sale. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 definitions data sheet identification product status definition objective specification preliminary specification product specification formative or in design preproduction product full production this data sheet contains the design target or goal specifications for product development. specifications may change in any manner without notice. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. philips semiconductors and philips electronics north america corporation register eligible circuits under the semiconductor chip protection act. ? copyright philips electronics north america corporation 1996 all rights reserved. printed in u.s.a.

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